1. Field of the Invention
The present invention relates to a lithography process, which is one process of manufacturing a semiconductor device. In particular, the present invention relates to a semiconductor device in which exposure of interconnects is carried out over the entire surface, and a method of manufacturing the same.
2. Description of the Related Art
Conventionally, in a process of manufacturing a semiconductor device, the entire surface of a wafer is exposed in a lithography process to make uniform the characteristic of the wafer surface (hereinafter, referred to as an entire surface shot). The foregoing entire surface shot has the following problem. As shown in FIG. 5, a chip T has a portion in which a chipped pattern (hereinafter, referred to as a defective chip portion) is generated. The chip T ranges over a portion on the periphery of a wafer S in which the resist is removed (hereinafter, referred to as a peripheral cut portion). In the lithography process of interconnections, the pattern scatters from the defective chip portion, resulting in a failure due to dust. In FIG. 5, there is shown an enlarged image A of the chip T.
Jpn. Pat. Appln. KOKAI Publication No. 6-275613 discloses the following technique. According to the technique, a step in an interconnection forming portion is reduced, and the film thickness of a resist pattern is prevented from being locally varied when interconnection patterns are formed. In this way, disconnection and pattern collapse are prevented. Moreover, Jpn. Pat. Appln. KOKAI Publication No. 7-297492 discloses the following technique. According to the technique, a substrate surface is processed into a concavo-convex shape periodically and smoothly changing. Thereafter, in the multi-layer process, the concavo-convex shape is hard to collapse; therefore, this serves to prevent resist pattern collapse. Moreover, Jpn. Pat. Appln. KOKAI Publication No. 11-68067 discloses the following technique. According to the technique, a plug connected with a lower layer interconnection through a contact hole or via hole formed in an interlayer insulating film is formed. Etching is carried out so that the upper surface of the interlayer insulating film becomes lower than the upper surface of the plug to leave the interlayer insulating film. In this way, pattern collapse is prevented.